Gated filter and sample hold circuit



Oct. 7, 1969 ms. HUGHES 3,471,719

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United States Patent 3,471,719 GATED FILTER AND SAMPLE HOLD CIRCUIT Richard Smith, Hughes, China Lake, Califi, assignor to the United States of America as represented by the Secretary of the Navy Filed July 13, 1966, Ser. No. 565,011 Int. Cl. H03k 17/26 US. Cl. 307-293 2 Claims ABSTRACT OF THE DISCLOSURE A circuit operable as either a gated filter wherein the gating signal controls the response time of the filter, or a sample hold to hold the last voltage level applied thereto. When the gating signal is at a low potential, the circuit charges and discharges through a small resistor yielding a fast filter reponse time. When the gating signal is at a high potential, the circuit charges and discharges through a large resistor yielding a slow filter response time. If the resistor through which the filter charges is removed from the circuit, the response time approaches infinity and a sample hold circuit results.

The invention described herein may be manufactured and used by or for the Government of the United States of America for governmental purposes without the payment of any royalties thereon or therefor.

In some applications, such as electronic processing of direction-finding information, tracking information, radar systems, etc., it is desirable to display the information received and to concomitantly slow the rate of such information for display purposes. Also, it sometimes is desired, in such applications, to hold a sample signal for a desired period of time.

Accordingly, it is a principal object of this invention to provide an eflicient transistor circuit arrangement for use as a gated filter circuit which can be operated at either of two separate gated filter time constants.

Another object of this invention is to provide a transistorized circuit of simple construction and having a follow-hold feature.

A further object of this invention is to provide such a circuit which has the feature of exhibiting no transient voltages during the gating operation from one time constant to another.

Still another object of this invention is to provide such a circuit that can be used either as a gated filter circuit or as a sample hold circuit.

Additional objects of the invention will become apparent from the following description, which is given primarily for purposes of illustration, and not limitation.

Stated in general terms, the objects of the invention are attained by providing a circuit coupled to a gate signal so that when a gate signal is at a low potential, such as ground potential, a condenser is charged and dis charged through a small resistor having a fast filter response time, by two transistors operated in push-pull relationship with respect to the resistor and condenser, and when the gate signal goes to a higher value, the condenser is charged and discharged through a larger resistor having a slow filter response time by the use of a third transistor while the first two transistors are isolated. If the large resistor is removed from the circuit, the filter response time of the circuit approaches infinity and a sample signal hold circuit is attained.

A more detailed description of a specific embodiment of the invention is given below with reference to the accompanying drawing, wherein:

FIGURE 1 is a schematic circuit diagram showing a specific embodiment of the basic gated filter circuit of the invention; and

FIG. 2 is a graph illustrating the response of a specific embodiment of the gated filter circuit of FIG. 1.

Normally, the gate 10 is at the lower potential, such as ground potential, and transistor Q and diodes D and D in the basic circuit of FIG. 1, are biased olf. Transistors Q and Q, are connected in push-pull relationship to charge and discharge capacitor C. When transistor Q, is biased on, a charge is pushed into capacitor C from input 11 via D Q D Q and R When transistor Q, is biased on, the charge is pulled from capacitor C to the value of the potential at input 11 via R Q D Q and D Thus push-pull operation of transistors Q and Q, is established. The driving impedance from push-pull transistors Q and Q, is quite small. Consequently, the time constant is due almost entirely to resistor R when the resistance of resistor R is at least ten times as great as that of resistor R The direct current levels at the emitters of push-pull transistors Q and Q, are quite close to the current input level at input 11, since the forward bias voltage across diode D V cancels V the baseemitter forward bias voltage of transistor Q VBEQ1 cancels VBEQ V cancels V and VBEQ2 cancels VBEQ4.

When the gate voltage at 10 goes to a higher value, such as a positive voltage in the present case, transistor Q is turned on. This results in driving the voltage at the emitter of transistor Q V to the lower, ground voltage, thus back-biasing V and V is driven positive, back-biasing V Transistors Q and Q also are turned 01f. With transistors Q Q Q and Q electrically removed from the circuit, capacitor C now is charged and discharged through the much larger resistor R Care should be taken to make certain that transistor Q looks into a large impedance, at least ten times that of R or the output at 12 will not be at a one-to-one ratio with the input at 11, that is, related linearly. Normally, the resistance of resistor R is made small for a fast filter response and that of resistor R is made large for a slow filter response.

Transistors Q and Q constitute a high input impedance-low output impedance output amplifier, where having unity gain, so that external circuitry will not affect the charge on capacitor C. The large input impedance is needed to avoid loading resistor R or resistor R The low output impedance is needed to drive low resistance loads. If the resistance value of resistor R is not extremely large, such as about 20K, transistors Q and Q can be replaced with a conventional Darlington.

FIG. 2 illustrates the operation of the circuit of FIG. 1 while employing the following circuit component values:

Q =2N9 1 6 R =2K Q =2N26 04 C: microfarads Alldiodes=1N9l6 V =+12 v.

The basic gated filter circuit of FIG. 1 can be used as a sample hold circuit by removing resistor R; from the circuit illustrated in FIG. 1. In such case, the filtering time approaches infinity, or a sample hold has been attained. When the gate signal at 10 is at ground level, capacitor C is charged to the input voltage entered at 11. When the gate is turned on, capacitor C will hold its charge. The decay time is dependent upon the resistance of the back-biased base-emitter junctions of the transistors Q and Q and the back-biased gate-source and gatedrain junctions of transistor Q Obviously, many other modifications and variations of the gated filter and sample hold circuit of the invention are possible in the light of the teachings given hereabove. It is therefore to be understood that the invention may be practiced otherwise than as specifically described and illustrated hereinabove.

What is claimed is:

1. A gated filter circuit which comprises:

(a) a capacitor coupled in the circuit for charging and discharging thereof;

(b) a low resistance coupled to the capacitor;

(c) two transistors coupled to the low resistance and the capacitor for charging and discharging the capacitor in push-pull relationship therewith through the low resistance;

(d) a higher resistance coupled to the capacitor; and

(e) a third transistor coupled to the higher resistance and the capacitor for charging and discharging the capacitor throught he higher resistance while the first two push-pull transistors are isolated from hte circuit.

2. A gated filter circuit according to claim 1, wherein:

(a) diode means are coupled with the third transistor to bias the transistor 01? when a gate signal is at ground potential so that the capacitor is charged and discharged through the low resistance by the first two transistors in push-pull relationship with the capacitor; and

References Cited UNITED STATES PATENTS 3,165,650 1/1965 White 307-314 3,211,926 10/ 1965 Frysinger 307-267 3,259,854 7/1966 Marcus et a1. 307-228 3,341,696 9/1967 Thaulow 328-78 ARTHUR GAUSS, Primary Examiner B. P. DAVIS, Assistant Examiner US. Cl. X.R. 

